Product Summary

The WS628128LLPG-70 is a high performance ,very low power CMOS Static random access memory organized as 131,072 words by 8 bits. The WS628128LLPG-70 is available in the JEDEC standard 32 pin 600mil plastic DIP and 450mil plastic SOP.

Parametrics

WS628128LLPG-70 absolute maximum ratings: (1)VTERM Terminal voltage with respect to GND: -0.5 to +6.0 V; (2)TBIAS Temperature under blas: -40 to +125℃; (3)TSTG Storage temperature: -60 to +150℃; (4)PT Power dissipation: 1.0 W; (5)IOUT DC Output current: 20 mA.

Features

WS628128LLPG-70 features: (1)very low power consumption; (2)high speed access time; (3)input levels are COMO-compatible; (4)automatic power down when chip is desdlected; (5)thren state outputs; (6)fully static operation; (7)data retention supply voltage as low as 1.5V; (8)easy expansion with CE2, CE1, and OE options; (9)all I/O pins are 5V tolerant.

Diagrams

WS628128LLPG-70 block diagram

WS6264
WS6264

Other


Data Sheet

Negotiable